Fundraising September 15, 2024 – October 1, 2024
About fundraising
books search
books
Fundraising:
17.8% raised
Log In
Log In
to access more features
personal recommendations
Telegram Bot
download history
send to Email or Kindle
manage booklists
save to favorites
Personal
Book Requests
Explore
Z-Recommend
Booklists
Most Popular
Categories
Contribution
Donate
Uploads
Litera Library
Donate paper books
Add paper books
Search paper books
Open LITERA Point
Terms search
Main
Terms search
search
1
FPGA Verilog 开发实战指南 基于Intel Cyclone IV (Part 2)
野火
sdram
钟
output
址
sys_rst_n
input
码
assign
fpga
verilog
cyclone
intel
www.firebbs.cn
yehuosm.tmall.com
坛
猫
cfg_data_reg
控
操
sys_clk
频
网
1bit
fifo
摄
i2c
negedge
框
parameter
sdram_dq
芯
posedge
介
sdram_addr
储
串
刷
wm8978
rst_n
描
驱
rd_en
键
绍
define
宽
wr_en
50mhz
vga
绘
Year:
2021
Language:
chinese
File:
PDF, 39.80 MB
Your tags:
0
/
5.0
chinese, 2021
2
FPGA Verilog开发实战指南:基于Inter Cyclone IV(进阶篇)2021
刘火良 杨森 张硕
钟
sdram
sys_rst_n
址
码
操
sys_clk
频
网
控
input
fifo
negedge
刷
output
posedge
assign
框
parameter
wm8978
介
录
芯
绍
摄
rst_n
沿
播
define
宽
crc
cfg_data_reg
储
init_end
绘
预
crc_data
rd_en
描
延
串
迟
wr_en
协
udp
idle
rmii
帧
详
50mhz
File:
PDF, 13.76 MB
Your tags:
5.0
/
1.0
3
FPGA Verilog开发实战指南:基于Inter Cyclone IV(进阶篇)2021
北京华章图文信息有限公司
刘火良 杨森 张硕
钟
sdram
sys_rst_n
址
码
操
sys_clk
频
网
控
input
fifo
negedge
刷
output
posedge
assign
框
parameter
wm8978
介
录
芯
绍
摄
rst_n
沿
播
define
宽
crc
cfg_data_reg
储
init_end
crc_data
绘
预
rd_en
描
延
串
迟
wr_en
协
udp
idle
rmii
帧
详
50mhz
Year:
2021
Language:
chinese
File:
EPUB, 13.87 MB
Your tags:
5.0
/
0
chinese, 2021
1
Follow
this link
or find "@BotFather" bot on Telegram
2
Send /newbot command
3
Specify a name for your chatbot
4
Choose a username for the bot
5
Copy an entire last message from BotFather and paste it here
×
×